As the density of integrated circuits continues to increase, the scaling down of the dimensions of semiconductor devices in a semiconductor integrated circuit has followed. Today, a dielectric layer in a semiconductor device, such as the gate dielectric layer of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has reduced in thickness into the nanometer range. On the other hand, supply voltages applied on a MOSFET gate electrode have scaled down much slower in order to maintain good device performance, such as minimum sub-threshold leakage current and minimum device delay. As a result, the electrical field in a gate dielectric layer has increased significantly with each device generation. Under such circumstances, the reliability of a gate dielectric layer is now regarded as more of an important issue than ever before. As an example, when an operating voltage is applied on a gate oxide layer, the oxide layer can be broken down at the point when a certain period of time has passed from the start of application of a gate voltage. As a result, the gate oxide layer looses the electrical insulating properties, causing the gate and the channel region to be electrically shorted, which, in turn, leads to the failure of a MOSFET. The time period mentioned above is generally referred to as gate oxide layer lifetime. Tests for determining the lifetime of a dielectric layer are generally called reliability tests.
Many different theoretical models were suggested to explain the time dependent dielectric breakdown (TDDB) of a gate dielectric layer. Two classes of breakdown mechanisms are described by most theories and are familiar to those skilled in the art. An intrinsic breakdown model suggested by experimental facts is as the following. When a bias is applied on a dielectric layer, for example, a gate oxide layer, carriers such as electrons in the channel region of an NMOS transistor, can gain energy under the high electric field and tunnel through the dielectric layer. The tunneling current increases very rapidly with the continuous reduction of the oxide layer thickness. These energetic electrons can generate electron/hole pairs in the oxide near the gate electrode (anode) through impact ionization. Holes thus created in the oxide may inject back into the substrate under the electrical field. This process creates numerous defects (energy traps) in the oxide layer. When defect density in oxide reaches some critical level, a conductive path from the gate electrode to the substrate is formed, which causes device failure. Extrinsic breakdown are breakdown events attributable to defects brought into the oxide during manufacturing processes. These defects may include oxide roughness, particles in oxide, etc. Extrinsic breakdown are electric field and temperature dependent and are usually observed as early failures compared with intrinsic breakdown.
FIG. 1 shows the time evolution of gate leakage current of a MOS transistor subjected to time dependent dielectric breakdown (TDDB) on a gate dielectric layer. The gate leakage current Ig increases gradually as defects are accumulated in the gate dielectric layer. This process ultimately leads to device breakdown as a conductive path is formed between the gate electrode and the substrate. The gate dielectric layer lifetime is labeled as Tbd in FIG. 1.
Reliability testing is usually conducted on a semiconductor device to guarantee the device performance remains within the device's specification for a determined period of time. In view of gate oxide breakdown, the generally adopted industry standard is that, after 10 years of operation at the nominal conditions (voltage and temperature) at most 100 devices per million can fail. In practice, reliability testing on a gate oxide is usually carried out in an “accelerated” manner where excess stress (voltage and/or current) is applied on the gate oxide to accelerate the breakdown process since reliability testing under operating conditions will take an impractically long period of time. Such accelerated testing is generally referred to as a “burn-in” test by those skilled in the art. Under high stresses of a burn-in test, the oxide accumulates defects faster and a device fails more quickly. A gate oxide failure distribution and an acceleration factor of the stress can be obtained from a burn-in condition. The lifetime of a gate oxide under operating conditions can then be obtained by “extrapolating” the distribution under burn-in conditions to the operating conditions. Many prior art methods of a TDDB burn-in test exist. Examples include constant voltage test, constant current test, ramp voltage test and ramp current test. To demonstrate the shortcomings of prior art test methodologies, a detailed description is given herein to the constant voltage TDDB test method of prior art as the following.
In a prior art TDDB test for extracting an acceleration factor and estimating an oxide layer lifetime, constant stress voltages are applied to a gate oxide layer through the conductive gate electrode and the semiconductor substrate. Periods of time between the start of stress voltage application and a corresponding accumulated breakdown rate are recorded and plotted such as shown in FIG. 2A. In FIG. 2A, the horizontal axis represents stress time for which a stress voltage is applied on an oxide layer, while the right-hand vertical axis represents the accumulated failure rate P due to time dependent dielectric breakdown (TDDB) of a gate oxide layer and the left-hand vertical axis represents the ln {−ln(1−p)} calculated from the accumulated failure rate P. In conducting a TDDB test using this method, semiconductor wafers with a plurality, usually dozens or even hundreds, of gate oxide reliability test samples identical in shape, size, thickness, and production process are prepared. These samples are divided into a few groups, usually three groups. Samples of each group are subjected to a pre-determined stress voltage of V1, V2 or V3 respectively, which is much higher than the maximum voltage Vmax applied on a gate oxide layer under normal operating conditions. Under such stress application, oxide layers of each group experience a time dependent dielectric breakdown and the number of failed oxide layers increases with the passage of time. In FIG. 2A, the circle points, square points and triangle points represent respectively the accumulated failure rate at the points of time when oxide layers of each group fail under the stress voltages V1, V2 or V3. Based on this data, regression lines from, for example, least squares fitting can be drawn in order to obtain the accumulated failure rate at certain point of time when oxide layers of each group are under respective stress voltages. Shown in FIG. 2A, the plotting has a stress time on the horizontal coordinate in logarithm scale and ln {−ln(1−p)} on the vertical coordinate. This is generally referred to as Weibull plotting since the accumulated failure rates ln {−ln(1−p)} of the oxide layers follow the so-called Weibull distribution, which, empirically, is in the form of straight line. As a result, the periods of time during which the accumulated failure rates P reaches 50% under a stress voltage can be obtained, which, as a widely accepted criterion, represents an estimation of oxide layer lifetime. In the current prior art method, the estimation of oxide layer lifetime under stress voltages V1, V2 and V3 are recorded at the points where the Weibull plots intersect the long horizontal dash line, which corresponds to the 50% accumulated failure rate due to time dependent dielectric breakdown of oxide layers and are labeled as T1, T2 and T3 respectively.
With the estimated oxide layer lifetime T1, T2 and T3 (time for 50% accumulated failure rate) obtained from FIG. 2A, oxide layer lifetime Tbd versus stress voltages are plotted as circle points as shown in FIG. 2B, where the estimated oxide layer lifetime T1, T2 and T3 are plotted in a logarithm scale on the vertical coordinate, while the stress voltages V1, V2 and V3 applied on the oxide layers are plotted in a linear scale on the horizontal coordinate. Empirically, the distribution of the circle points is in the form of a linear distribution and a linear regression line can be formed through proper fitting techniques, such as, least square fitting. Consequently, the oxide layer lifetime T can be approximated in the form of a linear function of applied voltage Vg. The slope of the straight line is extracted as a voltage acceleration factor. The estimated lifetime Tlife of an oxide layer under normal device operating conditions, e.g., Vmax=2.0 V, can be obtained by extrapolating this straight line into the operating voltage region to intersect with the dashed vertical line Vg=2.0 V, as shown in FIG. 2B. In this example, the estimated gate oxide lifetime Tlife is approximately 10 years.
Although an estimated oxide layer lifetime can be obtained through an “extrapolating” method as described in the above prior art method, TDDB tests employing an “extrapolating” scheme have some common drawbacks. First, a process condition change, in particular, changes relating to steps of forming a gate in a MOSFET will most likely change the quality of a gate oxide layer. Therefore, it is required to frequently conduct reliability testing, such as TDDB tests in an integrated circuit manufacturing environment in order to estimate the gate oxide lifetimes of devices from changed process conditions. Even though burn-in testing is employed to “accelerate” device failure, prior art test methods, such as the constant voltage method described in above example, still last for days or even weeks to obtain the voltage acceleration factor and estimated oxide layer lifetime. Due to this hindrance, in practice, TDDB tests are only conducted under a few stress voltages on a limited number of samples out of a manufactured batch. These limitations lead to poor statistics on test results. As a result, oxide layer lifetime obtained through the prior art method is, in general, stress voltage dependent. This drastically increases the errors in the voltage acceleration factor and estimated oxide layer lifetime.
On the other hand, when extrapolating the linear regression line into the operating voltage region to obtain oxide layer lifetime under normal device operating conditions, as shown in FIG. 2B, an assumption is made in that the oxide layer exhibits the same dielectric behaviors at low voltages (low oxide field) as those at stress voltages. Unfortunately, this assumption is very rough and produces large errors in the extraction of voltage acceleration factors and oxide layer lifetime estimation. As an example, the high electric field in an oxide layer under high stress voltages generates a large amount of heat, which causes the oxide layer to increase in temperature. This leads to a shorter time period between the application of stress voltages and the time dependent dielectric breakdown (TDDB) of the oxide layer, when compared to the oxide layer breakdown time period with the use of normal temperatures and operating voltages. In other words, the oxide layer lifetime estimated from a burn-in test tends to be shorter than the period of time an oxide layer can actually function within its specification under nominal operating conditions. On occasion, an estimation error can be as large as years. This problem can also lead to a major impact on the cost of a semiconductor device manufacturing facility, where devices with good reliability can be unfavorably downgraded or scrapped due to the overly conservative estimation on oxide layer lifetime from a burn-in test.
In view of these and other drawbacks in a prior art TDDB test method, there is a need for an improved method in measuring the time dependent dielectric breakdown (TDDB) on dielectric layers in a practically short period of time, and in obtaining a voltage acceleration factor and oxide layer lifetime estimation value which are practically highly precise.